ARMv7-A 那些事 - 5.CP15协处理器
 2023.10.01    |      ARMv7-A    |     AilsonJack    |     暂无评论    |     32 views
By: AilsonJack
Date: 2023-10-01
个人博客: http://www.only2fire.com/
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background-color: #f5f8fa; background-image: linear-gradient( 180deg , hsla(0, 0%, 100%, 0.8), hsla(0, 0%, 100%, 0)); }</style><title>ARMv7-A 那些事 - 5.CP15协处理器</title><h2 id="协处理器概述">协处理器概述</h2><p>ARM架构通过支持协处理器来扩展处理器的功能。ARM架构的处理器支持最多16个协处理器,通常称为CP0~CP15。下述的协处理器被ARM用于特殊用途:</p><ul class=" list-paddingleft-2"><li><p>CP15:提供系统控制功能,主要用于配置MMU、TLB和Cache等功能。</p></li><li><p>CP14:主要用于控制系统Debug功能。</p></li><li><p>CP10、CP11:两个协处理器一起提供了对浮点运算和向量操作的支持,这两个协处理器主要用于控制和配置浮点功能和高级SIMD指令扩展。</p></li><li><p>其他协处理器被ARM保留用于将来使用。</p></li></ul><p>本文主要说说CP15协处理器。</p><h2 id="cp15协处理器总览">CP15协处理器总览</h2><p>CP15是系统控制协处理器,主要用于对ARM处理器核心支持的许多特性功能进行配置。CP15协处理器支持16个32位主寄存器(primary register),命名为c0~c15。c0~c15主寄存器各自又有多个32位的物理寄存器(physical register)。CP15协处理器的大多数寄存器不能在USR模式下访问,只能在除USR模式外的其他模式下访问。下面列出c0~c15中比较常用的寄存器:</p><p></p><figure><table><thead><tr class="firstRow"><th style="text-align:center;">primary register</th><th style="text-align:center;">physical register</th><th style="text-align:center;">描述</th></tr></thead><tbody><tr><td style="text-align:center;">c0</td><td style="text-align:center;">MIDR</td><td style="text-align:center;">主ID寄存器,用于记录版本信息</td></tr><tr><td style="text-align:center;">c0</td><td style="text-align:center;">MPIDR</td><td style="text-align:center;">多核处理器情况下,提供一种方法来唯一标识集群中的各个核心</td></tr><tr><td style="text-align:center;">c1</td><td style="text-align:center;">SCTLR</td><td style="text-align:center;">系统控制寄存器</td></tr><tr><td style="text-align:center;">c1</td><td style="text-align:center;">ACTLR</td><td style="text-align:center;">辅助控制寄存器</td></tr><tr><td style="text-align:center;">c1</td><td style="text-align:center;">CPACR</td><td style="text-align:center;">协处理器访问控制寄存器,控制访问除了CP14和CP15的协处理器</td></tr><tr><td style="text-align:center;">c1</td><td style="text-align:center;">SCR</td><td style="text-align:center;">安全配置寄存器,被TrustZone使用</td></tr><tr><td style="text-align:center;">c2、c3</td><td style="text-align:center;">TTBR0</td><td style="text-align:center;">一级转换页表基址寄存器0</td></tr><tr><td style="text-align:center;">c2、c3</td><td style="text-align:center;">TTBR1</td><td style="text-align:center;">一级转换页表基址寄存器1</td></tr><tr><td style="text-align:center;">c2、c3</td><td style="text-align:center;">TTBCR</td><td style="text-align:center;">页表转换控制寄存器</td></tr><tr><td style="text-align:center;">c5、c6</td><td style="text-align:center;">DFSR</td><td style="text-align:center;">数据异常(Data Fault)状态寄存器</td></tr><tr><td style="text-align:center;">c5、c6</td><td style="text-align:center;">IFSR</td><td style="text-align:center;">指令异常(Instruction Fault)状态寄存器</td></tr><tr><td style="text-align:center;">c5、c6</td><td style="text-align:center;">DFAR</td><td style="text-align:center;">数据异常(Data Fault)地址寄存器</td></tr><tr><td style="text-align:center;">c5、c6</td><td style="text-align:center;">IFAR</td><td style="text-align:center;">指令异常(Instruction Fault)地址寄存器</td></tr><tr><td style="text-align:center;">c7</td><td style="text-align:center;">branch predictor</td><td style="text-align:center;">cache和分支预测管理功能</td></tr><tr><td style="text-align:center;">c7</td><td style="text-align:center;">barrier</td><td style="text-align:center;">数据和指令屏障操作</td></tr><tr><td style="text-align:center;">c8</td><td style="text-align:center;">TLB</td><td style="text-align:center;">TLB操作</td></tr><tr><td style="text-align:center;">c9</td><td style="text-align:center;">performance monitors</td><td style="text-align:center;">性能监视器</td></tr><tr><td style="text-align:center;">c12</td><td style="text-align:center;">VBAR</td><td style="text-align:center;">提供非监视模式处理异常的异常基地址</td></tr><tr><td style="text-align:center;">c12</td><td style="text-align:center;">MVBAR</td><td style="text-align:center;">提供监视模式处理异常的异常基地址</td></tr><tr><td style="text-align:center;">c13</td><td style="text-align:center;">CONTEXTIDR</td><td style="text-align:center;">上下文ID寄存器</td></tr><tr><td style="text-align:center;">c15</td><td style="text-align:center;">CBAR</td><td style="text-align:center;">配置基址寄存器,为GIC和本地时钟类型外设提供基地址</td></tr></tbody></table></figure><p></p><p>在CP15协处理器中,c0~c15每个主处理器下面有多个物理寄存器,上述表格只列出了部分常用的物理寄存器。</p><h2 id="协处理器操作指令">协处理器操作指令</h2><p>ARMv7-A体系结构的处理器提供了<code>MRC</code>和<code>MCR</code>指令用于对协处理器进行读写操作。<code>MRC</code>指令用于将CP15协处理器中的寄存器数据读取到ARM通用寄存器中。<code>MCR</code>指令用于将ARM通用寄存器中的数据写入到CP15协处理器的寄存器中。</p><h3 id="mrc">MRC</h3><p><code>MRC</code>指令的语法如下所示:</p><pre class="md-fences md-end-block md-fences-with-lineno ty-contain-cm modeLoaded" spellcheck="false" lang="asm">MRC{cond}&nbsp;coproc,&nbsp;opc1,&nbsp;Rt,&nbsp;CRn,&nbsp;CRm{,&nbsp;opc2}</pre><p><code>cond</code>为条件码。</p><p><code>coproc</code>为协处理器名称,CP0~CP15协处理器分别对应名称p0~p15。</p><p><code>opc1</code>为协处理器要执行的操作码,取指范围为0~7。</p><p><code>Rt</code>为ARM通用寄存器,用于存储读取到的协处理器寄存器数据。</p><p><code>CRn</code>为协处理器寄存器,对于CP15协处理器来说,<code>CRn</code>取值范围为c0~c15。</p><p><code>CRm</code>为协处理器寄存器,对于CP15协处理器来说,通过<code>CRm</code>和<code>opc2</code>一起来确定<code>CRn</code>对应的具体寄存器。</p><p><code>opc2</code>为可选的协处理器执行操作码,取指范围为0~7,当不需要的时候要设置为0。</p><p><code>MRC</code>指令使用示例如下:</p><pre class="md-fences md-end-block md-fences-with-lineno ty-contain-cm modeLoaded" spellcheck="false" lang="asm">#&nbsp;读取主ID寄存器&nbsp;MIDR&nbsp;的数据到&nbsp;R0&nbsp;中. MRC&nbsp;p15,&nbsp;0,&nbsp;R0,&nbsp;c0,&nbsp;c0,&nbsp;0</pre><h3 id="mcr">MCR</h3><p><code>MCR</code>指令的语法如下所示:</p><pre class="md-fences md-end-block md-fences-with-lineno ty-contain-cm modeLoaded" spellcheck="false" lang="asm">MCR{cond}&nbsp;coproc,&nbsp;opc1,&nbsp;Rt,&nbsp;CRn,&nbsp;CRm{,&nbsp;opc2}</pre><p><code>cond</code>为条件码。</p><p><code>coproc</code>为协处理器名称,CP0~CP15协处理器分别对应名称p0~p15。</p><p><code>opc1</code>为协处理器要执行的操作码,取指范围为0~7。</p><p><code>Rt</code>为ARM通用寄存器,用于存储要写入到协处理器寄存器中的数据。</p><p><code>CRn</code>为协处理器寄存器,对于CP15协处理器来说,<code>CRn</code>取值范围为c0~c15。</p><p><code>CRm</code>为协处理器寄存器,对于CP15协处理器来说,通过<code>CRm</code>和<code>opc2</code>一起来确定<code>CRn</code>对应的具体寄存器。</p><p><code>opc2</code>为可选的协处理器执行操作码,取指范围为0~7,当不需要的时候要设置为0。</p><p><code>MCR</code>指令使用示例如下:</p><pre class="md-fences md-end-block md-fences-with-lineno ty-contain-cm modeLoaded" spellcheck="false" lang="asm">#&nbsp;将&nbsp;R0&nbsp;中的配置数据写入到&nbsp;SCTLR MCR&nbsp;p15,&nbsp;0,&nbsp;R0,&nbsp;c1,&nbsp;c0,&nbsp;0</pre><h2 id="cp15协处理器主寄存器组成">CP15协处理器主寄存器组成</h2><p>CP15协处理器有c0~c15总共16个主寄存器,在每个主寄存器下面,又有多个物理寄存器。下图总结了CP15协处理器的寄存器组织形式:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154213347337780.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154213347337780.png&#39;)"/></p><p>上图对于<code>MRC</code>和<code>MCR</code>指令所要使用到的一些参数都标明了,对于想要访问CP15协处理器相关寄存器,只需要看图填写好参数就行了。下面具体列一下c0~c15各个主寄存器的组成。</p><h2 id="cp15协处理器c0寄存器组成">CP15协处理器c0寄存器组成</h2><p>主寄存器c0主要提供ID相关的功能,c0寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154213597224739.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154213597224739.png&#39;)"/></p><h2 id="cp15协处理器c1寄存器组成">CP15协处理器c1寄存器组成</h2><p>主寄存器c1主要提供系统控制相关的功能,c1寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154213277737913.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154213277737913.png&#39;)"/></p><p>在CP15协处理器的寄存器中,系统控制寄存器SCTLR是被访问的比较多的寄存器。对SCTLR寄存器的访问需要在PL1或者更高的特权等级。SCTLR寄存器的位关系如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154213639187633.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154213639187633.png&#39;)"/></p><figure><table><thead><tr class="firstRow"><th>位</th><th>标志</th><th>说明</th></tr></thead><tbody><tr><td>30</td><td>TE</td><td>Thumb异常使能,控制在异常发生时(包括reset),将会进入哪种指令集,0:ARM指令集,1:Thumb指令集</td></tr><tr><td>27</td><td>NMFI</td><td>不可屏蔽的FIQ支持,0:软件可以通过写CPSR.F位来屏蔽FIQ,1:软件不可以通过写CPSR.F位来屏蔽FIQ</td></tr><tr><td>25</td><td>EE</td><td>在进入异常处理时的大小端模式配置,0:小端,1:大端</td></tr><tr><td>22</td><td>U</td><td>表明是否使用对齐模式</td></tr><tr><td>21</td><td>FI</td><td>FIQ配置使能</td></tr><tr><td>13</td><td>V</td><td>选择异常向量表基址,0:0x00000000,1:0xffff0000</td></tr><tr><td>12</td><td>I</td><td>指令cache使能</td></tr><tr><td>11</td><td>Z</td><td>分支预测使能</td></tr><tr><td>2</td><td>C</td><td>数据cache使能</td></tr><tr><td>1</td><td>A</td><td>对齐检查使能</td></tr><tr><td>0</td><td>M</td><td>MMU使能</td></tr></tbody></table></figure><p></p><h2 id="cp15协处理器c2-c3寄存器组成">CP15协处理器c2 c3寄存器组成</h2><p>主寄存器c2和c3主要提供内存保护和内存控制相关的功能,c2和c3寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154214469455948.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154214469455948.png&#39;)"/></p><h2 id="cp15协处理器c4寄存器组成">CP15协处理器c4寄存器组成</h2><p>在任何基于ARMv7实现的处理器中,协处理器CP15的c4寄存器没有被使用。</p><h2 id="cp15协处理器c5-c6寄存器组成">CP15协处理器c5 c6寄存器组成</h2><p>主寄存器c5和c6主要提供内存系统错误上报功能,c5和c6寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154214936167448.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154214936167448.png&#39;)"/></p><h2 id="cp15协处理器c7寄存器组成">CP15协处理器c7寄存器组成</h2><p>主寄存器c7主要提供cache维护,地址转换和内存屏障操作相关的功能,c7寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154214941201185.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154214941201185.png&#39;)"/></p><h2 id="cp15协处理器c8寄存器组成">CP15协处理器c8寄存器组成</h2><p>主寄存器c8主要提供TLB维护相关的功能,c8寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154224839881562.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154224839881562.png&#39;)"/></p><h2 id="cp15协处理器c9寄存器组成">CP15协处理器c9寄存器组成</h2><p>主寄存器c9保留用于分支预测,cache和TCM操作,c9寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154224988463658.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154224988463658.png&#39;)"/></p><h2 id="cp15协处理器c10寄存器组成">CP15协处理器c10寄存器组成</h2><p>主寄存器c10主要提供内存重映射和TLB控制相关的功能,c10寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154212140805801.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154212140805801.png&#39;)"/></p><h2 id="cp15协处理器c11寄存器组成">CP15协处理器c11寄存器组成</h2><p>主寄存器c11保留用于TCM DMA操作,c11寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154224202827477.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154224202827477.png&#39;)"/></p><h2 id="cp15协处理器c12寄存器组成">CP15协处理器c12寄存器组成</h2><p>主寄存器c12提供安全扩展功能,c12寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154224354111821.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154224354111821.png&#39;)"/></p><h2 id="cp15协处理器c13寄存器组成">CP15协处理器c13寄存器组成</h2><p>主寄存器c13提供进程ID、上下文ID和线程ID处理功能,c13寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154225904351735.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154225904351735.png&#39;)"/></p><h2 id="cp15协处理器c14寄存器组成">CP15协处理器c14寄存器组成</h2><p>主寄存器c14保留用于通用定时器功能,c14寄存器的组成如下图所示:</p><p style="text-align:center"><img src="/uploads/AilsonJack/2023.10.01/154225378291291.png" onclick="preview_image(&#39;/uploads/AilsonJack/2023.10.01/154225378291291.png&#39;)"/></p><h2 id="cp15协处理器c15寄存器组成">CP15协处理器c15寄存器组成</h2><p>主寄存器c15由处理器实现决定。</p><p>这里只是简单的将CP15各个主寄存器的组成列出来了,方便在使用<code>MRC</code>和<code>MCR</code>指令配置CP15主寄存器时,查看指令各个参数的设置,以及对照配置的具体寄存器,至于寄存器的具体内容由于篇幅原因就不列出来了,CP15寄存器的细节可以参考ARMv7AR手册的B3.17章节内容。</p><!--!doctype-->
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ARMv7-A 那些事 - 5.CP15协处理器  |  说好一起走
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